Chemical mechanical polishing is increasingly being used as a planarizing process for semiconductor device layers, especially for devices having multi-level design and smaller semiconductor fabrication processes, for example, below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-level semiconductor device, including planarizing levels of a device containing both dielectric and metal portions to achieve global planarization for subsequent processing of overlying levels.
A limitation of CMP is its high dependency on pattern density, which results in a non-uniform planarization of large and small features. Under polish, over polish and non-uniform polish affect the resistivity of a damascene-formed trench metal system.
Another prior art method includes using a multi-zone head to control Cu CMP within wafer uniformity. After Cu deposition on a wafer, the wafer may be loaded into a CMP apparatus wherein the wafer may be subjected to the CMP process in steps using different platens within the CMP apparatus. The multi-zone head allows for differing pressures across the CMP head. While multi-zone processing may produce satisfactory results in a dielectric layer CMP process, multi-zone processing may not produce satisfactory results in a Cu CMP process. FIG. 1 shows the differences between a multi-zone head and a single zone head. A disadvantage of this prior art method is that the within wafer uniformity for Cu structure resistivity may not be controlled within necessary limits.
Another prior art method includes taking measurements of a sample wafer to determine the post etch uniformity. The slurry feed arm is adjusted to a subsequent dispensing position such that the slurry is dispensed over the polishing pad at a position that compensates for previous process non-uniformities and provides for a more uniform polished layer. A disadvantage of this prior art method is that the sample measurements may not be indicative of the wafer run being processed. Another disadvantage is the cost of delay while measurements are taken and interpreted.